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?001 fairchild semiconductor corporation ITF86130SK8T rev. a file number 4798.5 ITF86130SK8T 14a, 30v, 0.0078 ohm, n-channel, logic level, power mosfet packaging so8 (jedec ms-012aa) symbol features ultra low on-resistance -r ds(on) = 0.0078 ?, v gs = 10v -r ds(on) = 0.010 ?, v gs = 4.5v -r ds(on) = 0.012 ?, v gs = 4.0v gate to source protection diode simulation models - temperature compensated pspice and saber electrical models - spice and saber thermal impedance models - www.intersil.com peak current vs pulse width curve transient thermal impedance curve vs board mounting area switching time vs r gs curves branding dash 1 2 3 4 5 source(2) drain(8) source(1) drain(7) drain(6) drain(5) source(3) gate(4) ordering information part number package brand ITF86130SK8T so8 86130 note: when ordering, use the entire part number. ITF86130SK8T is available only in tape and reel. absolute maximum ratings t a = 25 o c, unless otherwise speci?d ITF86130SK8T units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 30 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 30 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20 v drain current continuous (t a = 25 o c, v gs = 10v) (figure 2) (note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t a = 25 o c, v gs = 4.5v) (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t a = 100 o c, v gs = 4.5v) (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d continuous (t a = 100 o c, v gs = 4.0v) (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i dm 14.0 12.0 7.0 7.0 figure 4 a a a a a power dissipation (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 20 w mw/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t l package body for 10s, see tech brief tb370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c notes: 1. t j = 25 o c to 125 o c. 2. 50 o c/w measured using fr-4 board with 0.76in 2 (490.3mm 2 ) copper pad at 10s. caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only ratin g and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. data sheet september 2000
?001 fairchild semiconductor corporation ITF86130SK8T rev. a electrical speci?ations t a = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 11) 30 - - v zero gate voltage drain current i dss v ds = 30v, v gs = 0v - - 10 a gate to source leakage current i gss v gs = 20v - - 10 ua on state specifications gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 10) 1.5 - 2.5 v drain to source on resistance r ds(on) i d = 14.0a, v gs = 10v (figures 8, 9) - 0.0058 0.0078 ? i d = 7.0a, v gs = 4.5v (figure 8) - 0.007 0.010 ? i d = 7.0a, v gs = 4.0v (figure 8) - 0.008 0.012 ? thermal specifications thermal resistance junction to ambient r ja pad area = 0.76 in 2 (490.3 mm 2 ) (note 2) - - 50 o c/w pad area = 0.054 in 2 (34.8 mm 2 ) (figure 20) - - 152 o c/w pad area = 0.0115 in 2 (7.42 mm 2 ) (figure 20) - - 189 o c/w switching specifications (v gs = 4.5v) turn-on delay time t d(on) v dd = 15v, i d = 7.0a,v gs = 4.5v, r gs = 4.7 ? (figures 14, 18, 19) -23-ns rise time t r -84-ns turn-off delay time t d(off) -33-ns fall time t f -42-ns switching specifications (v gs = 10v) turn-on delay time t d(on) v dd = 15v, i d = 14.0a, v gs = 10v, r gs = 5.1 ? (figures 15, 18, 19) -14-ns rise time t r - 106 - ns turn-off delay time t d(off) -49-ns fall time t f - 69 - ns gate charge specifications total gate charge q g(tot) v gs = 0v to 10v v dd = 15v, i d = 12.0a, i g(ref) = 1.0ma, (figures 13, 16, 17) -5884nc gate charge at 5v q g(5) v gs = 0v to 5v - 31.5 - nc threshold gate charge q g(th) v gs = 0v to 1v - 3 - nc gate to source gate charge q gs - 9.5 - nc gate to drain ?iller?charge q gd -12-nc capacitance specifications input capacitance c iss v ds = 25v, v gs = 0v, f = 1mhz (figure 12) - 3050 - pf output capacitance c oss - 675 - pf reverse transfer capacitance c rss - 285 - pf source to drain diode speci?ations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 12.0a - 0.79 - v reverse recovery time t rr i sd = 12.0a, di sd /dt = 100a/ s - 33 - ns reverse recovered charge q rr i sd = 12.0a, di sd /dt = 100a/ s - 32 - nc ITF86130SK8T
?001 fairchild semiconductor corporation ITF86130SK8T rev. a typical performance curves figure 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs ambient temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capability t a , ambient temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 6 9 12 15 50 75 100 125 150 0 25 i d , drain current (a) t a , ambient temperature ( o c) v gs = 4.0v, r ja = 189 o c/w v gs = 10v, r ja = 50 o c/w 3 0.01 0.1 1 3 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 0.001 10 -5 t, rectangular pulse duration (s) z ja , normalized thermal impedance single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 r ja = 50 o c/w 100 1000 2000 10 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 -5 i dm , peak current (a) t, pulse width (s) r ja = 50 o c/w transconductance may limit current in this region i = i 25 150 - t a 125 for temperatures above 25 o c derate peak current as follows: t a = 25 o c v gs = 4.5v ITF86130SK8T
?001 fairchild semiconductor corporation ITF86130SK8T rev. a figure 5. forward bias safe operating area figure 6. transfer characteristics figure 7. saturation characteristics figure 8. drain to source on resistance vs gate voltage and drain current figure 9. normalized drain to source on resistance vs junction temperature figure 10. normalized gate threshold voltage vs junction temperature typical performance curves (continued) 10 10 100 500 1 1 100 s 10ms 1ms v ds , drain to source voltage (v) i d , drain current (a) limited by r ds(on) area may be operation in this t j = max rated t a = 25 o c single pulse 100 r ja = 50 o c/w 0 10 20 50 60 2.0 2.5 3.0 3.5 4.0 i d , drain current (a) v gs , gate to source voltage (v) pulse duration = 80 s duty cycle = 0.5% max v dd = 15v t j = 25 o c t j = 150 o c t j = -55 o c 40 30 10 20 50 60 0 0.2 0.4 0.6 1.0 0 i d , drain current (a) v ds , drain to source voltage (v) v gs = 3v v gs = 10v t a = 25 o c v gs = 3.5v pulse duration = 80 s duty cycle = 0.5% max 40 30 0.8 v gs = 5v v gs = 4.5v v gs = 4v i d = 5a 4 8 16 20 246810 v gs , gate to source voltage (v) i d = 14a r ds(on) , drain to source on resistance (m ? ) pulse duration = 80 s duty cycle = 0.5% max 12 0.7 1.0 1.3 1.6 -80 -40 0 40 80 120 160 normalized drain to source t j , junction temperature ( o c) on resistance v gs = 10v, i d = 14a pulse duration = 80 s duty cycle = 0.5% max 0.4 0.6 1.0 1.2 -80 -40 0 40 80 120 160 normalized gate t j , junction temperature ( o c) v gs = v ds , i d = 250 a threshold voltage 0.8 ITF86130SK8T
?001 fairchild semiconductor corporation ITF86130SK8T rev. a figure 11. normalized drain to source breakdown voltage vs junction temperature figure 12. capacitance vs drain to source voltage note: refer to intersil application notes an7254 and an7260. figure 13. gate charge waveforms for constant gate current figure 14. switching time vs gate resistance figure 15. switching time vs gate resistance typical performance curves (continued) 0.9 1.0 1.1 1.2 -80 -40 0 40 80 120 160 t j , junction temperature ( o c) normalized drain to source breakdown voltage i d = 250 a 200 1000 5000 0.1 1.0 10 30 c, capacitance (pf) v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss = c gs + c gd c oss ? c ds + c gd c rss = c gd 0 2 4 6 8 10 0 20 30405060 v gs , gate to source voltage (v) v dd = 15v q g , gate charge (nc) i d = 12a i d = 2a waveforms in descending order: 10 200 300 400 0 1020304050 0 switching time (ns) r gs , gate to source resistance ( ? ) v gs = 4.5v, v dd = 15v, i d = 7.0a t d(off) t r t f t d(on) 100 100 200 300 400 0 1020304050 0 switching time (ns) r gs , gate to source resistance ( ? ) v gs = 10v, v dd = 15v, i d = 14a t d(off) t r t d(on) t f ITF86130SK8T
?001 fairchild semiconductor corporation ITF86130SK8T rev. a thermal resistance vs. mounting pad area the maximum rated junction temperature, t jm , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, p dm , in an application. therefore the applications ambient temperature, t a ( o c), and thermal resistance r ja ( o c/w) must be reviewed to ensure that t jm is never exceeded. equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. in using surface mount devices such as the so8 package, the environment in which it is applied will have a signi?ant in?ence on the parts current and maximum power dissipation ratings. precise determination of p dm is complex and in?enced by many factors: 1. mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. the number of copper layers and the thickness of the board. 3. the use of external heat sinks. 4. the use of thermal vias. 5. air ?w and board orientation. 6. for non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. intersil provides thermal information to assist the designers preliminary application evaluation. figure 20 de?es the r ja for the device as a function of the top copper (component side) area. this is for a horizontally positioned fr-4 board with 1oz copper after 1000 seconds of steady state power with no air ?w. this graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. pulse applications can be evaluated using the intersil device spice thermal test circuits and waveforms figure 16. gate charge test circuit figure 17. gate charge waveforms figure 18. switching time test circuit figure 19. switching time waveform r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 1v q g(5) v gs = 5v q g(tot) v gs = 10v v ds v gs i g(ref) 0 0 q gs q gd v gs 0v r gs r l dut + - v gs v ds t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 (eq. 1) p dm t jm t a ?? ?? z ja ------------------------------ - = ITF86130SK8T
?001 fairchild semiconductor corporation ITF86130SK8T rev. a model or manually utilizing the normalized maximum transient thermal impedance curve. displayed on the curve are r ja values listed in the electrical speci?ations table. the points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, p dm . thermal resistances corresponding to other copper areas can be obtained from figure 20 or by calculation using equation 2. r ja is de?ed as the natural log of the area times a coef?ient added to a constant. the area, in square inches is the top copper area including the gate and source pads. the transient thermal impedance (z ja ) is also effected by varied top copper board area. figure 21 shows the effect of copper pad area on single pulse transient thermal impedance. each trace represents a copper pad area in square inches corresponding to the descending list in the graph. spice and saber thermal models are provided for each of the listed pad areas. copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. for pulse widths less than 100ms the transient thermal impedance is determined by the die and package. therefore, ctherm1 through ctherm5 and rtherm1 through rtherm5 remain constant for each of the thermal models. a listing of the model component values is available in table 1. (eq. 2) r ja 83.2 23.6 area () ln = figure 20. thermal resistance vs mounting pad are a 120 160 200 240 0.1 1.0 80 0.01 r ja = 83.2 - 23.6 * ln (area) 152 o c/w - 0.054in 2 189 o c/w - 0.0115in 2 r ja ( o c/w) area, top copper area (in 2 ) figure 21. thermal impedance vs mounting pad area 30 60 90 120 150 0 10 -1 10 0 10 1 10 2 10 3 t, rectangular pulse duration (s) z ja , thermal copper board area - descending order 0.04 in 2 0.28 in 2 0.52 in 2 0.76 in 2 1.00 in 2 impedance ( o c/w) ITF86130SK8T
?001 fairchild semiconductor corporation ITF86130SK8T rev. a pspice electrical model .subckt ITF86130SK8T 2 1 3 ; rev 23 nov 1999 ca 12 8 2.00e-9 cb 15 14 2.15e-9 cin 6 8 2.70e-9 dbody 7 5 dbodymod dbreak 5 11 dbreakmod desd1 91 9 desd1mod desd2 91 7desd2mod dplcap 10 5 dplcapmod ebreak 11 7 17 18 37.19 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1.0e-9 lgate 1 9 1.04e-9 lsource 3 7 1.29e-10 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 3.50e-4 rgate 9 20 1.13 rldrain 2 5 10 rlgate 1 9 9 10.4 rlsource 3 7 1.29 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 4.55e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*650),2))} .model dbodymod d (is = 4.33e-12 rs = 3.91e-3 trs1 = 1.01e-3 trs2 = 1.11e-6 cjo = 2.02e-9 tt = 3.02e-8 m = 0.50) .model dbreakmod d (rs = 1.08e-1 trs1 = 1.01e-3 trs2 = 1.04e-7) .model desd1mod d (bv = 16.4 tbv1= -2.50e-3 n= 21 rs = 100) .model desd2mod d (bv = 16.1 tbv1= -2.50e-3 n= 21 rs = 100) .model dplcapmod d (cjo = 1.35e-9 is = 1e-30 m = 0.50) .model mmedmod nmos (vto = 2.28 kp = 10.00 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 1.13) .model mstromod nmos (vto = 2.65 kp = 275 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.92 kp = 0.10 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 11.3 rs = 0.1) .model rbreakmod res (tc1 = 9.98e-4 tc2 = 1.01e-7) .model rdrainmod res (tc1 = 3.78e-2 tc2 = 4.99e-5) .model rslcmod res (tc1 = 4.07e-3 tc2 = 2.25e-5) .model rsourcemod res (tc1 = 1.00e-3 tc2 = 0) .model rvthresmod res (tc1 = -2.79e-3 tc2 = -9.65e-6) .model rvtempmod res (tc1 = -1.90e-3 tc2 = 0) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -4.0 voff= -0.6) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -0.6 voff= -4.0) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -0.5 voff= 0) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0 voff= -0.5) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 18 22 desd1 desd2 91 6 ITF86130SK8T
?001 fairchild semiconductor corporation ITF86130SK8T rev. a saber electrical model rev 23 nov 1999 template ITF86130SK8T n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (is = 4.33e-12,rs=3.91e-3,trs1=1.01e-3,trs2=1.11e-6, cjo = 2.02e-9, tt = 3.02e-8, m = 0.50) dp..model dbreakmod = (rs=1.08e-1,trs1=1.01e-3,trs2=1.04e-7) dp..model desd1mod = (bv=16.4,tbv1=-2.50e-3,n1=21, rs=100) dp..model desd2mod = (bv=16.1,tbv1=-2.50e-3,n1=21, rs=100) dp..model dplcapmod = (cjo = 1.35e-9, is = 1e-30, m = 0.50) m..model mmedmod = (type=_n, vto = 2.28, kp = 10, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.65, kp = 275, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.92, kp = 0.10, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -0.6) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -0.6, voff = -4.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -0.5) c.ca n12 n8 = 2.00e-9 c.cb n15 n14 = 2.15e-9 c.cin n6 n8 = 2.70e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.desd1 n91 n9 = model=desd1mod dp.desd2 n91 n7 = model=desd2mod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.00e-9 l.lgate n1 n9 = 1.04e-9 l.lsource n3 n7 = 1.29e-10 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 9.98e-4, tc2 = 1.01e-7 res.rdrain n50 n16 = 3.50e-4, tc1 = 3.78e-2, tc2 = 4.99e-5 res.rgate n9 n20 = 1.13 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 10.4 res.rlsource n3 n7 = 1.29 res.rslc1 n5 n51 = 1e-6, tc1 = 4.07e-3, tc2 = 2.25e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 4.55e-3, tc1 = 1.00e-3, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.90e-3, tc2 = 0 res.rvthres n22 n8 = 1, tc1 = -2.79e-3, tc2 = -9.65e-6 spe.ebreak n11 n7 n17 n18 = 37.19 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/650))** 2)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rvtemp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mweak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rslc2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 desd1 desd2 91 ITF86130SK8T
?001 fairchild semiconductor corporation ITF86130SK8T rev. a spice thermal model rev 11 nov 1999 ITF86130SK8T copper area = 0.04 in 2 ctherm1 th 8 2.0e-3 ctherm2 8 7 5.0e-3 ctherm3 7 6 1.0e-2 ctherm4 6 5 4.0e-2 ctherm5 5 4 9.0e-2 ctherm6 4 3 1.2e-1 ctherm7 3 2 0.5 ctherm8 2 tl 1.3 rtherm1 th 8 0.1 rtherm2 8 7 0.5 rtherm3 7 6 1.0 rtherm4 6 5 5.0 rtherm5 5 4 8.0 rtherm6 4 3 26 rtherm7 3 2 39 rtherm8 2 tl 55 saber thermal model copper area = 0.04 in 2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 2.0e-3 ctherm.ctherm2 8 7 = 5.0e-3 ctherm.ctherm3 7 6 = 1.0e-2 ctherm.ctherm4 6 5 = 4.0e-2 ctherm.ctherm5 5 4 = 9.0e-2 ctherm.ctherm6 4 3 = 1.2e-1 ctherm.ctherm7 3 2 = 0.5 ctherm.ctherm8 2 tl = 1.3 rtherm.rtherm1 th 8 = 0.1 rtherm.rtherm2 8 7 = 0.5 rtherm.rtherm3 7 6 = 1.0 rtherm.rtherm4 6 5 = 5.0 rtherm.rtherm5 5 4 = 8.0 rtherm.rtherm6 4 3 = 26 rtherm.rtherm7 3 2 = 39 rtherm.rtherm8 2 tl = 55 } rtherm6 rtherm8 rtherm7 rtherm5 rtherm4 rtherm3 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 7 junction case 8 th rtherm2 rtherm1 ctherm7 ctherm8 table 1. thermal models component 0.04 in 2 0.28 in 2 0.52 in 2 0.76 in 2 1.0 in 2 ctherm6 1.2e-1 1.5e-1 2.0e-1 2.0e-1 2.0e-1 ctherm7 0.5 1.0 1.0 1.0 1.0 ctherm8 1.3 2.8 3.0 3.0 3.0 rtherm6 26 20 15 13 12 rtherm7 39 24 21 19 18 rtherm8 55 38.7 31.3 29.7 25 ITF86130SK8T
?001 fairchild semiconductor corporation ITF86130SK8T rev. a ITF86130SK8T ms-012aa 8 lead jedec ms-012aa small outline plastic package ms-012aa 12mm tape and reel a a 1 e e 1 e b d l h x 45 o 2 0 o -8 o c 0.004 in 0.10 mm 56 0.155 4.0 0.275 7.0 0.050 1.27 0.024 0.6 0.060 1.52 minimum recommended footprint for surface-mounted applications 1 symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a 1 0.004 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 - c 0.0075 0.0098 0.19 0.25 - d 0.189 0.1968 4.80 5.00 2 e 0.2284 0.244 5.80 6.20 - e 1 0.1497 0.1574 3.80 4.00 3 e 0.050 bsc 1.27 bsc - h 0.0099 0.0196 0.25 0.50 - l 0.016 0.050 0.40 1.27 4 notes: 1. all dimensions are within allowable dimensions of rev. c of jedec ms-012aa outline dated 5-90. 2. dimension ??does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.006 inches (0.15mm) per side. 3. dimension ? 1 ?does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.010 inches (0.25mm) per side. 4. ? is the length of terminal for soldering. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. controlling dimension: millimeter. 7. revision 8 dated 5-99. user direction of feed l c 2.0mm 4.0mm 1.75mm 1.5mm dia. hole 8.0mm 12mm cover tape 330mm 50mm 13mm 18.4mm 12.4mm general information 1. 2500 pieces per reel. 2. order in multiples of full reels only. 3. meets eia-481 revision ? specifications. access hole 40mm min.
trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. pacman? pop? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher smart start? star* power? stealth? fast fastr? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? microwire? optologic? optoplanar? rev. h ? acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? uhc? ultrafet? vcx? ? ?

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